| Offset | Name | R/W | Description | |--------|---------------|-----|--------------------------------------------| | 0x00 | VERSION | R | Hardware version (0x0100) | | 0x04 | CONTROL | RW | Enable/Disable, Reset, Interrupt mask | | 0x08 | STATUS | R | Busy, DMA active, Key error, Auth fail | | 0x0C | DESCRIPTOR_PTR| RW | 64-bit address of descriptor ring | | 0x10 | DOORBELL | WO | Write 1 to start processing | | 0x14 | INT_STATUS | RC | Interrupt source (DMA done, error) |
—This paper presents the architecture of a PCI Express (PCIe) integrated controller capable of performing real-time AES-256-GCM encryption and decryption. The controller operates as a PCIe Endpoint, presenting a memory-mapped interface to the host. By utilizing Direct Memory Access (DMA) and pipeline cryptography, the design achieves a throughput of >10 Gbps with sub-100µs latency. Implementation on a Xilinx Kintex UltraScale FPGA demonstrates robust side-channel resistance and full compliance with the PCIe 3.0 x4 standard. pci encryption decryption controller
The PCI Encryption/Decryption Controller works by: | Offset | Name | R/W | Description