LP-11 (stop) → LP-01 → LP-00 → HS-0 (first bit)
(v2.0 improvement) – clock lane enters LP-11 when idle, reducing power.
| Type | Limit (2.5 Gbps) | |--------------------------|------------------------| | Lane-to-lane skew | ≤ 0.2 UI (80 ps) | | Intra-lane skew (Dp-Dn) | ≤ 0.05 UI (20 ps) | | Clock-data jitter (Tj) | ≤ 0.3 UI (120 ps) |
LP-11 (stop) → LP-01 → LP-00 → HS-0 (first bit)
(v2.0 improvement) – clock lane enters LP-11 when idle, reducing power. mipi d phy 2.0 specification
| Type | Limit (2.5 Gbps) | |--------------------------|------------------------| | Lane-to-lane skew | ≤ 0.2 UI (80 ps) | | Intra-lane skew (Dp-Dn) | ≤ 0.05 UI (20 ps) | | Clock-data jitter (Tj) | ≤ 0.3 UI (120 ps) | LP-11 (stop) → LP-01 → LP-00 → HS-0 (first bit) (v2