This report details the design, implementation, and simulation of a 4-bit synchronous binary up-counter using Xilinx Vivado Design Suite. The design utilizes Verilog Hardware Description Language (HDL) to model flip-flops and combinational logic. The objective is to create a counter that increments on the rising edge of a clock signal, includes an active-high enable signal, and a synchronous reset functionality. Simulation results confirm the design meets the required logic specifications.
Download Vivado HLx WebPACK (it’s free for students). vivado student
Vivado Student Edition is a powerful tool for students and educators to learn and teach digital design and FPGA development. Its free and accessible nature makes it an excellent choice for hands-on learning and real-world experience. With its comprehensive features and industry-standard tools, Vivado Student Edition prepares students for success in the field of digital design and beyond. Simulation results confirm the design meets the required
// Clock generation: 10ns period (100MHz) initial begin clk = 0; forever #5 clk = ~clk; end Its free and accessible nature makes it an